1. Field of the Invention
Non-volatile semiconductor memory systems having multiple power states are described. More specifically, components and methods for improving utilization and reducing power requirements of flash memory systems that include sub- or near-threshold components are described.
2. Description of the Related Art
In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single integrated circuit (“IC”), or distributed across multiple ICs. Depending on cost and other known considerations, the discrete electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice.
Shown in FIG. 1 is a typical general purpose computer system 10. Although not all of the electronic facilities illustrated in FIG. 1 may be operable in the sub-threshold or near-threshold domains in any particular embodiment, some, at least, may be advantageously adapted to do so, with concomitant reductions in system power dissipation. In particular, in recently-developed battery-powered mobile systems, such as smart-phones and the like, many of the discrete components typical of desktop or laptop devices illustrated in FIG. 1 are integrated into a single IC. The Related Application 1 discloses several circuits adapted to operate in the sub-threshold domain.
Shown by way of example in FIG. 2 is a typical single-chip microcontroller unit (“MCU”) 12 comprising: a central processing unit (“CPU”) 14; at least one volatile memory (“VM”) facility 16; at least one non-volatile memory (“NVM”) facility 18; one or more timers (“Timers”) 20; at least one input/output master (“I/O Master”) facility 22; at least one input/output slave (“I/O Slave”) facility 24; at least one analog to digital converter (“ADC”) facility 26; a power management unit (“PMU”) 28; and a clock generator (“Clock Generator”) facility 30. A system bus (“System Bus”) 32 interconnects the several MCU facilities 14-30, and a clock distribution bus (“Clock Bus”) 34 distributes all clock signals developed by the Clock Generator 30 to the respective clocked facilities. As is known, development of the several clocks is generally controlled by information written to one or more control registers within Clock Generator 30 via the System Bus 32, and by system power state information typically provided by the PMU 28.
As is known, non-volatile solid-state memory systems are widely used in a variety of mobile and handheld devices, notably smart-phones, tablets, laptops, and other consumer electronics products. Non-volatile memory, which can include embedded or stand-alone charge-based flash memory (“Flash”), phase change memory, resistive RAM (“RRAM”), or magneto-resistive memory (“MRAM”), is of particular advantage for battery operated mobile devices that have limited available power. Typically, electronic systems in such devices have processors, MCUs, or other electronic controllers that support architected power states (e.g., an active state, a stand-by or sleep state, a deep-sleep state, etc.). As compared to active states, the power consumption in these electronic systems can be significantly reduced when the device is maintained in stand-by or sleep states.
In some applications, a number of the circuits associated with the non-volatile memory facility need to be kept alive to allow for fast memory access when a memory read operation has been requested, e.g., by the CPU 14 switching from a stand-by or sleep state to an active state. Unfortunately, the current consumed by these circuits often results in unacceptable power consumption in sleep or stand-by mode. However, if these circuits are simply turned off, then the time required to turn-on the circuits, reach stability, and begin normal memory read/write operations may be unacceptably long.